Semiconductor component manufacturers are constantly striving to increase the performance of their products, while decreasing their cost of manufacture. Because semiconductor components such as microprocessors and memory elements can contain up to a billion transistors, the focus for increasing performance and lowering manufacturing cost has been to shrink the sizes of the transistors making up the semiconductor components. This has introduced surface topographies that have decreased the planarity of the surfaces. In addition, shrinking the transistors increases their surface roughness. Non-planar surfaces that arise during intermediate manufacturing steps can create imperfections such as voids in layers subsequently formed over the non-planar surface. These imperfections degrade device performance. FIG. 1 illustrates a portion of a prior art Electrically Erasable and Programmable Read Only Memory Device (“EEPROM”) 10 during an intermediate stage of manufacture. EEPROM 10 comprises a semiconductor substrate 12 having a major surface 14 and Shallow Trench Isolation (“STI”) structures 16. A layer of dielectric material 18 is formed on major surface 14. Floating gates 20 and 22 are disposed on portions of dielectric layer 18 and are spaced apart from each other by a gap. The initial width of the gap is indicated by arrows 24. An Oxide-Nitride-Oxide (“ONO”) dielectric structure 19 is formed on floating gates 20 and 22. A layer of polysilicon 28 having a surface 30 is disposed on dielectric structure 19. Because floating gates 20 and 22 create a surface topography over surface 14, a void 32 forms in the portion of polysilicon layer 28 between floating gates 20 and 22, i.e., in the region of the gap. Void 32 degrades the performance of the devices comprising EEPROM 10 and, therefore, it degrades the performance of EEPROM 10.
In addition, when layers such as polysilicon layer 28 are formed, their surfaces are not smooth but have a surface roughness associated with them. Typically, this surface roughness has a Root Mean Square (RMS) surface roughness of greater than 75 Angstroms (Å). As the transistors are made smaller, this surface roughness adversely affects subsequent photolithographic steps. For example, a photoresist layer 34 deposited on polysilicon layer 28 having a rough surface 30, will have a “wavy,” i.e., non-planar, surface. When photoresist layer 34 is exposed to light, the waviness increases the reflection of light within photoresist layer 34, which degrades the quality of the pattern formed in the photoresist layer. For small geometry devices, this degradation may lower the performance of the transistors or decrease their yield.
Accordingly, what is needed is a semiconductor component and method for its manufacture, wherein the semiconductor component has void-free layers with smooth surfaces.